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PICTURE Project

CONSORTIUM

Published on 1 February 2021
With a strong history of collaboration, PICTURE gathers an experienced and complementary consortium - with a strong history of collaboration - with two academic actors (CEA-LETI & Mines Saint-Etienne) and two world-wide industrial partners (STMicroelectronics & IDEMIA). 

The project is coordinated by Pierre-Alain MOËLLIC (CEA-LETI).

LETI_LOGO.jpgCEA Tech is CEA’s technology research unit develops a broad portfolio of technologies particularly for ICTs and security. Associated to CEA-LETI (Grenoble) the Laboratory of Secured Object and Physical System (LSOSP) is colocated at Grenoble and Gardanne. At Gardanne, the team takes benefit from a vast cluster of academic and industrial partners and is a joint team with Mines Saint-Etienne. The team is currently involved in several programs (Fr, EU) developing its recognized expertise in secure integrated circuits against physical attacks and secure complex systems with HW and SW requirements. 

Participation: Led by Pierre-Alain Moëllic and Simon Pontié, CEA-LETI is the coordinator and participates in all the WPs with a main scientific focus on optimal embedding of neural network, algorithmic attacks and defenses and fault injection analysis for integrity threats.


Logo_Mines_Saint-Étienne.svgMines Saint-Etienne (MSE). Research takes place in the Secured Architecture and Systems (SAS) department of the Centre Microélectronique de Provence (CMP, Gardanne). The team haa strong experience in the design and the characterization of circuits and systems on chips with leading equipment dedicated to physical analysis (side-channel and fault injection). The team works closely with CEA in many projects related to secure integrated circuits.

Participation: Led by Jean-Max Dutertre and Olivier Potin, MSE proposes its expertise in physical attacks on complex platforms, the exploitation of side-channel leakages and the fault injection technics. As the leader of WP3. MSE also suggests and evaluates the impact of defense strategies.


STMICRO.pngSTMicroelectronics (ST, ST Rousset SAS) is a world-wide independent provider of semiconductors. The major strategic objective of ST is to provide solutions for smart driving and IoT. Within STMicroelectronics, ST (Rousset) SAS is in charge of the microcontrolers and secure numeric solutions. With CEA and MSE, ST carried out several research programs related to hardware security. 


Participation: ST is supporting and developing various Artificial Intelligence solutions for its MCU and MPU based on both software and hardware implementation of DNN. Led by Laurent Sourgen with a dedicated team of experts (S.Wuidart, M. Lisart), MCU architects and support team, ST will support the definition of use cases (rather around time based variables) using embedded processors (Cortex M and A). ST will follow up anticipated analysis and attacks, as well as evaluating the implementability of potential countermeasures initialy software based, but also influencing future hardware accelerator architectures.

visuel_idemia-logo2.jpgIDEMIASupported by 12,000 employees worldwide (2,000 in R&D), IDEMIA is the merger between Oberthur Technologies and Morpho. Today a leading player in the identification and authentication sector, the group serves clients in 180 countries and provides services to financial institutions, mobile operators, IoT, citizen identity and public security. IDEMIA is involved in numerous collaborative projects (EU, Fr) with a close collaboration with the academic partners of PICTURE. 


Participation: With a strong expertise in ML-based system and alerted to DNN security, IDEMIA (led by S. Gentric) will work on providing biometric facial recognition networks optimized (e.g,. via quantization and architecture) for embedded platforms with possibly TEE running constraints. IDEMIA will participate in analyzing the performance and outcome of proposed attacks and the embedded DNN robustness according to their architecture, as well as evaluating software countermeasures and their impacts on real use-cases.